1. Field of the Invention
The present invention relates generally to avionics systems and more particularly to an improved multi-core processor architecture for use in an integrated modular avionics (IMA) system.
2. Description of the Related Art
Modern onboard avionics networks serve to provide data transfer between various components of an aircraft. Avionics systems typically have a variety of systems that provide data to processing components of the aircraft or exchange data among one or more components of the aircraft. For example, a variety of avionics modules may gather avionics data (e.g., sensors detecting speed, direction, external temperature, control surface positions, and the like) that is routed by the avionics system via an avionics network to one or more aircraft components such as displays, monitoring circuits, processors, and the like.
In some aircraft systems, the avionics network may be constructed with an Aeronautical Radio Inc. (ARINC) 429 data bus capable of supporting communication between many components. More recently, Ethernet networks have been used in avionic network environments by leveraging Commercial Off The Shelf (COTS) technology to increase bandwidth and reduce cost.
Ethernet type networks have been used in communication networks for implementing communication among various network components. An Ethernet network may be used to send or route data in a digital form by packets or frames. Each packet contains a set of data, and the packet is generally not interpreted while sent through the Ethernet network. In an avionics network environment, the Ethernet network typically has different components that subscribe to the avionics network and connect to each other through switches. Each network subscriber can send packets in digital form, at controlled rates, to one or more other subscribers. When a switch receives the packets, the switch determines the destination equipment and directs or switches the packets to such equipment.
Such Ethernet networks may include ARINC-664 based networks. In a switched full-duplex Ethernet type network, the term “full-duplex” refers to sending and receiving packets at the same time on the same link, and the term “switched” refers to the packets being switched in switches on appropriate outputs. However, the ARINC-664 network uses multiple switches and redundant paths to route data, point-to-point or point-to-multipoint across the switches. Typically, remote data concentrators are connected using a wired ARINC-664 network.
Current Integrated Modular Avionics (IMA) architectures are reliant on data concentrators to bring the aircraft system I/O into the IMA system. The data concentrators are located remotely within the aircraft to reduce the wire weight of the system. Typically they are connected by the IMA backbone bus.
Present applicants Daniel Mazuk and David Miller are co-applicants of U.S. Ser. No. 12/151,249, filed May 5, 2008, entitled “Passive Optical Avionics Network,” which is directed to a passive optical avionics network system and method that comprises: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU. An integrated modular avionics (IMA) system in accordance with the network system comprises: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU. U.S. Ser. No. 12/151,249 is incorporated herein by reference, for all purposes, in its entirety.
Some of the locations of the remote data concentrators (RDC's) are a very hostile environment or the backbone bus wire needs to travel through the hostile environment to get to the RDC.
These difficult installations could benefit from a wireless link to/from the IMA backbone bus.
Multi-core processors today share multiple internal resources which causes the certification to be problematic. The internal IP of the multi-core processor is held with the supplier and is not shared with the users so a detail safety analysis of the shared resources cannot be performed.
All IMA architecture suppliers have either used single core processors or shut down the extra cores of a multi-core processor because they cannot prove the safety of using the extra cores thus the use of multi-core processors are not certifiable.